Field of the Invention
The invention relates to a RAM (Random Access Memory) circuit having a memory cell array in the form of a matrix-type configuration of rows and columns. The total number of the rows includes a number of regular rows and a number of redundant rows and each row is assigned a word line for activating and deactivating the memory cells of the relevant row.
In RAMs of the aforementioned type, each word line is connected to a dedicated driver containing a plurality of switching elements, usually field-effect transistors (FETs), which respond to control signals in order to put the relevant word line either at an activation potential or at a deactivation potential. Only in the activated state of a word line are the memory cells of the associated row conditioned for a write or read access, the access itself being effected via bit lines assigned to the individual columns of the cell array.
In the layout of an integrated circuit, the aforementioned word line drivers are arranged in a driver array along one of the column-parallel edges of the cell array where the input-side ends of the word lines are situated. In large scale integrated memory chips, the pitch of the word lines (e.g. 0.17 xcexcm center-to-center distance) is significantly smaller than the widthxe2x80x94running in the column directionxe2x80x94of each individual transistor of the drivers. Consequently, each driver extends of necessity over the width of a plurality of word lines in the column direction. This makes it necessary to arrange in each case a plurality of drivers offset (that is to say spatially xe2x80x9cone behind the otherxe2x80x9d) in the row direction, the number p of the drivers in each of these groups being at least as large as the number of word lines which find space within the required width of a driver. Each driver group is thus assigned to a group of p adjacent word lines.
For reasons of memory organization and with the aim of economic utilization of the chip area, it is advisable and customary to choose the number p of drivers or word lines per group (that is to say the xe2x80x9cgroup strengthxe2x80x9d) such that the total number n of regular rows or word lines is divisible by p without remainder and, consequently, an integer number g=n/p of groups is fully occupied. In this case, each word line is uniquely selectable through the use of an input address which is applied to the memory chip and is hierarchically composed of exactly one of g possible group addresses which identifies the relevant word line group, and exactly one of p possible position addresses which identifies the position of the word line within the respective group. Accordingly, a word line decoder is constructed hierarchically in two stages: a 1-out-of-g group decoder which responds to the group address addresses the respective driver group, and each of the g driver groups is configured, for its part, as a 1-out-of-p decoder which responds to the position address in order to drive the addressed word line within the relevant group.
For layout reasons the drivers must be spatially arranged such that they occupy locations in a regular pattern. Each location is determined by an X coordinate measured in the row direction and a Y coordinate measured in the column direction. Given a number of rows n+r and a group strength p, there are p possible X coordinates and (n+r)/p possible Y coordinates, if n+r is an integer multiple of p, with n being the number of regular rows and r being the number of redundant rows.
The redundant rows and word lines serve for repairing the cell array, i.e. for replacing defective rows, if the test run of the memory has demonstrated such defects. This replacement is done, in principle, by reprogramming the addresses of the word lines of defective rows through the use of generally known fuse technology within the decoding device into addresses of redundant word lines, so that the input addresses themselves can be maintained unaltered.
The reprogramming of the addresses is simpler, the fewer bits of an input address have to be reprogrammed. The fuse technology used for this purpose becomes the least complicated if, in the case of a defective row, all p rows of the relevant group of rows are replaced by a whole group of p redundant rows, because then only bits of the group address need to be changed. For this reason, the number r of redundant word lines is usually likewise an integer multiple of the group strength p, so that the same hierarchical address structure (group addresses with in each case p position addresses) as for the regular word lines holds true. Although a groupwise repair entails the risk of a certain degree of waste, this can be kept within limits if it is taken into consideration that defects often occur in clusters anyway, that is to say simultaneously encompass a plurality of adjacent word lines. Nevertheless, the practice of groupwise repair requires that, for a given number of regular rows, more redundant rows have to be provided than in cases where it is possible to repair individual rows or bundles of rows which are smaller than the group strength p.
Important criteria for the number of redundant rows to be chosen are the associated increase in area and the exploitation or defect probability of the regular rows. An excessively small number of redundancies leads to memories that cannot be completely repaired, while too many redundant rows increase the chip area unnecessarily. In the case of large memories (e.g. above 256 MB), it is allowable, under certain circumstances, to replace an entire group of e.g. p=4 regular rows by an equally sized group of redundant rows (so-called quadruple redundancy) even if only one row in the group is defective. In the case of smaller memories, however, it is advisable to subdivide the repair possibilities more finely. Thus, in the case of a 128 MB-DRAM, for example, it is recommendable to provide, for 1024 regular rows in each case, 12 redundant rows and the possibility of pairwise repair, so that the repair supply includes 6 pairs.
In earlier times, the redundant rows were positioned in a common contiguous block at an outer edge of the cell array. Advantages may be afforded, however, by departing from this practice and arranging the quantity of redundant rows as two separate subsets in two different sections of the cell array.
One of these advantages is ensuring a xe2x80x9ctopologically correctxe2x80x9d repair if a so-called bit line twist is present in the cell array. This is understood as the known measure of transposing selected bit line cores at a location within the cell array, the so-called xe2x80x9ctwist regionxe2x80x9d, in order to reduce the risk of undesirable signal coupling. The twist has the effect that the sections of the cell array have a different data topology on both sides of the twist region, i.e. the pattern of the assignment between the polarity of the memory cell charge and the data evaluation on the bit lines is different on one side of the twist region than on the other side. Only if redundant rows are present on each side can a defective row always be replaced by a redundant row of the same data topology.
Furthermore, it may be expedient, even with no twist present, to position redundant rows at both edges of the cell array. This reduces the defect probability for regular rows, because the defect risk is greater at the edges than in the interior of the cell array.
Dividing the redundant rows between two sections of the cell array poses no problems if the number of such rows in each of the two sections is an integer multiple of the group strength p. However, this requires the total number r of redundant rows to be an integer multiple of p. This means, however, e.g. given the group strength p=4, that the possible total number of redundant word lines is limited to 16 or 24 or 32, etc. A problem arises if one wishes to choose a different number (e.g. 12) for the reasons presented further above. This is because the situation then arises wherein the number of rows is not an integer multiple of p in each of the two sections, unless the total number of all the regular rows is also made not equal to a multiple of p. This last is undesirable, however.
If, in the first of the two sections, the number of rows is a number k less than an integer multiple of p (and, correspondingly, the number of rows in the second section is k greater or pxe2x88x92k less than an integer multiple of p), a continuously regular layout of the word line drivers within the driver array is no longer possible. This is due to the fact that the X coordinates of the k drivers which lack the integer multiple of p in the first section do not correspond to the X coordinates of the pxe2x88x92k drivers which lack an integer multiple of p in the second section.
Since the resultant layout problem has not been satisfactorily solved hitherto, all that has remained in practice has been the possibility either of making the number of redundant word lines equal to an even-numbered multiple of the group strength, or of combining all the redundant word lines in one of the two sections. However, as stated, the former prohibits an optimal choice of the number of redundant rows and thus limits the possibility for reducing the area requirement of the cell array, and the latter means dispensing with the abovementioned advantage of a reduced defect risk for regular word lines and, in the case of a bit line twist that is present, dispensing with the possibility of an always topologically correct repair.
It is accordingly an object of the invention to provide a RAM circuit which overcomes the above-mentioned disadvantages of the heretofore-known RAM circuits of this general type and which has redundant rows and which has both the advantages which result from a number of redundant rows that deviates from an even-numbered multiple of the group strength, and the advantages which result from positioning the redundant rows in two separate sections.
With the foregoing and other objects in view there is provided, in accordance with the invention, a RAM circuit, including:
a memory cell array including memory cells, rows and columns;
the rows and columns defining a row direction and a column direction and forming a matrix configuration, a total number of the rows being an integer multiple of an integer number p greater than 1, the rows including an integer number n of regular rows and an integer number r of redundant rows;
regular word lines and redundant word lines;
each of the rows being assigned a respective one of the regular and redundant word lines for activating and deactivating the memory cells in a relevant one of the rows;
the memory cell array having column-parallel side edges;
a driver array disposed parallel to one of the column-parallel side edges of the memory cell array, the driver array including a plurality of drivers, a respective one of the drivers being contact-connected to a respective one of the regular and redundant word lines for driving the respective one of the regular and redundant word lines;
the memory cell array and the driver array occupying a given space subdivided into a first section and a second section;
an integer number n1 greater than 0 of the regular rows and an integer number r1 greater than 0 of the redundant rows being disposed in the first section, and n1+r1 of the drivers being disposed in the first section;
an integer number n2 greater than 0 of the regular rows and an integer number r2 greater than 0 of the redundant rows being disposed in the second section, where n1+r1 is by an integer number k less than an integer multiple of the integer number p, and n2+r2 of the drivers being disposed in the second section;
the n1+r1 of the drivers disposed in the first section each occupying a respective location allocated thereto in a regular two-dimensional first pattern of locations, the locations in the first pattern having Y coordinates measured in the column direction, the Y coordinates of the locations in the first pattern being uniformly spaced apart, each of the locations in the first pattern having one of p possible X coordinates in the row direction, adjacent ones of the locations in the first pattern with a same one of the X coordinates being spaced apart by a distance in the column direction equal to p times a spacing distance of the Y coordinates of the locations in the first pattern;
the n2+r2 of the drivers disposed in the second section each occupying a respective location allocated thereto in a regular two-dimensional second pattern of locations, the locations in the second pattern having Y coordinates measured in the column direction, the Y coordinates of the locations in the second pattern being uniformly spaced apart, each of the locations in the second pattern having one of the p possible X coordinates in the row direction, adjacent ones of the locations in the second pattern with a same one of the X coordinates being spaced apart by a distance in the column direction equal to p times a spacing distance of the Y coordinates of the locations in the second pattern;
the first section having an outer edge with pxe2x88x92k last ones of the locations in the first pattern disposed in the outer edge; and
the locations in the first pattern being occupied without any vacancies within the first section and, within the second section, pxe2x88x92k of the locations in the second pattern being unoccupied locations with X coordinates identical to the X coordinates of the pxe2x88x92k last ones of the locations in the first pattern.
In other words, the invention is realized in a RAM circuit containing a memory cell array and a driver array. The memory cell array forms a matrix-type configuration of rows and columns, the total number of rows being an integer multiple of an integer p greater than 1 and being composed of a number n of regular rows and a number r of redundant rows, each row being assigned a regular or redundant word line for the activation and deactivation of the memory cells of the relevant row. The driver array is arranged parallel to one of the column-parallel side edges of the cell array and contains, for each word line, a driver that is contact-connected to precisely this word line, for driving the latter.
According to the invention, the space occupied by the cell array and by the driver array is subdivided into two sections, in the first section of which there is situated a number n1 greater than 0 of regular rows and a number r1 greater than 0 of redundant rows and in the second section of which there is situated a number n2 greater than 0 of regular rows and a number r2 greater than 0 of redundant rows, where n1+r1 is by a number k smaller than an integer multiple of p. Each of the n1+r1 drivers of the first section occupies a location allocated to it in a regular two-dimensional first pattern of locations whose Y coordinates measured in the column direction are uniformly spaced apart and each of which has one of p possible X coordinates in the row direction, adjacent locations with the same X coordinate having a distance in the column direction which is equal to p times the distance of the Y coordinates. Each of the n2+r2 drivers of the second section occupies a location allocated to it in a regular two-dimensional second pattern of locations whose Y coordinates measured in the column direction are uniformly spaced apart and each of which has one of the p possible X coordinates in the row direction, adjacent locations with the same X coordinate having a distance in the column direction which is equal to p times the distance of the Y coordinates. The locations of the first pattern are occupied without any gaps or vacancies within the first section and, within the second section, pxe2x88x92k locations of the second pattern are unoccupied, to be precise those whose X coordinates are identical to the X coordinates of the pxe2x88x92k last locations of the pattern which are occupied at the outer edge of the first section.
The features of the invention presented above ensure that none of the drivers has to occupy a location which does not fit the layout pattern of the drivers. The layout problem indicated above is thus solved. This problem and the way in which this problem is solved according to the invention are explained in more detail below with reference to drawings. The invention is preferably, but not exclusively, used for dynamic RAMs (DRAMs).
According to another feature of the invention, the memory cell array includes a bit line twist region; and the first and second sections lie on respective different sides of the bit line twist region.
According to another feature of the invention, the first and second sections each have a respective outer edge such that at least a subset of the redundant rows are disposed in the outer edge.
According to yet another feature of the invention, in each of the first and second sections, the redundant rows form a contiguous block.
According to a further feature of the invention, in each of the first and second sections, all of the redundant rows situated in a respective one of the first and second sections form a contiguous block at an outer edge of the respective one of the first and second sections; and within the second section, the pxe2x88x92k unoccupied locations in the second pattern lie between locations occupied by the drivers for the regular rows and locations occupied by the drivers for the redundant rows.
According to another feature of the invention, the integer number n1 is equal to the integer number n2, the integer number r1 is equal to the integer number r2; and the integer number n1, the integer number r2 and the integer number r are integer multiples of the integer number p.
According to another feature of the invention, the integer number p is an integer power of 2.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a RAM with redundant word lines, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.